Dynamic random access memories (DRAMs) typically include an array of stacked or deep trench capacitors for storing data as charge. Memory cell access field-effect transistors (FETs) are provided for switchably accessing the charge storage nodes of these storage capacitors. DRAMS that are fabricated on bulk silicon substrates are susceptible to "soft errors" resulting from alpha particles that stray from the environment or integrated circuit package. Such alpha particles penetrate the bulk silicon substrate, where they generate large numbers of minority charge carriers. These minority charge carriers are collected at reverse-biased pn-junctions of the access FETs, where they perturb the data that is stored as charge on the storage capacitors. For immunity to such soft errors, large trench or stacked storage capacitors are required in bulk silicon DRAMs in order to store large quantities of charge. These capacitors constitute an estimated 30% of DRAM fabrication cost.
By contrast, DRAMs that are fabricated using semiconductor-on-insulator (SOI) substrates are more immune to soft errors. SOI substrates typically comprise a thin layer of active semiconductor, such as silicon, on an underlying insulating layer, such as silicon dioxide (SiO.sub.2). Memory cells are fabricated upon the thin active semiconductor layer. The number of minority charge carriers generated by a penetrating alpha particle decreases along with the available semiconductor volume. Since SOI substrates present less available semiconductor volume than bulk silicon substrates, fewer minority carriers are generated in the thin active semiconductor layer. As a result, SOI DRAMs are less prone to disturbance of data charges resulting from alpha particles. Thus, storage capacitors in an SOI DRAM can be an estimated one-tenth the size of storage capacitors in a bulk silicon DRAM. The difference may become even greater as technology advances and dimensions become smaller. Bulk silicon DRAMs will require comparatively larger-valued storage capacitances. Such larger storage capacitances will likely occupy more integrated circuit area or require a high dielectric constant insulating material, thereby increasing fabrication cost and complexity. SOI DRASMs, having smaller-valued storage capacitances, will be cheaper than bulk silicon DRAMs.
A further consideration is a body bias voltage that is provided to the body portion of the memory cell access FET to improve memory cell operation. The body bias voltage allows the memory cell to operate from a low power supply voltage, such as 1.5 volts, from which a gate voltage controlling the access FET is derived. Turning the access FET on to transfer data to or from the storage capacitor requires a gate voltage in excess of a turn-on threshold voltage. However, low power supply voltages, such as 1.5 volts, may not provide sufficient overdrive voltage in excess of the threshold voltage to fully turn on the access FET. The gate voltage required for turning on the access FET can be reduced by controlling the body bias voltage. The body bias voltage also controls a subthreshold leakage current of the access FET. The access FET is turned off when data is stored as charge on the storage capacitor. During the time period when the access FET is turned off, the subthreshold leakage current removes some of the stored data charges from the storage node of the storage capacitor. The body bias voltage value controls the reverse bias of the access FET pn junction that is coupled to the storage node. By increasing the reverse bias of such pn junctions, the subthreshold leakage current is reduced. Without a proper body bias voltage, the subthreshold leakage current would lead to short data retention times.
Providing the body bias voltage to the memory cell access FETs requires a conductive body line that interconnects the access FET body contacts to receive the body bias voltage. The body line, as well as bit line, word line, and other such conductors all occupy integrated circuit surface area. To increase DRAM data storage density, the surface area of each memory cell, referred to as its "footprint", must be minimized. However, conventional memory cells typically require word lines and body lines on the upper surface of the memory cell, requiring surface area in addition to that of the memory cell storage capacitor.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a DRAM or other semiconductor memory device having a memory cell providing an access FET word and body lines that occupy reduced integrated circuit area. There is a further need in the art for a compact radiation tolerant memory cell that allows the use of smaller storage capacitors to increase memory data storage density and to reduce integrated circuit manufacturing costs.